KGL15ZR71A104MT

Low Inductance Capacitors Introduction The signal integrity characteristics of a Power Delivery Network (PDN) are becoming critical aspects of board level and semiconductor package designs due to higher operating frequencies, larger power demands, and the ever shrinking lower and upper voltage limits around low operating voltages. These power system challenges are coming from mainstream designs with operating frequencies of 300MHz or greater, modest ICs with power demand of 15 watts or more, and operating voltages below 3 volts. The classic PDN topology is comprised of a series of capacitor stages. Figure 1 is an example of this architecture with multiple capacitor stages. An ideal capacitor can transfer all its stored energy to a load instantly. A real capacitor has parasitics that prevent instantaneous transfer of a capacitor’s stored energy. The true nature of a capacitor can be modeled as an RLC equivalent circuit. For most simulation purposes, it is possible to model the characteristics of a real capacitor with one capacitor, one resistor, and one inductor. The RLC values in this model are commonly referred to as equivalent series capacitance (ESC), equivalent series resistance (ESR), and equivalent series inductance (ESL). The ESL of a capacitor determines the speed of energy transfer to a load. The lower the ESL of a capacitor, the faster that energy can be transferred to a load. Historically, there has been a tradeoff between energy storage (capacitance) and inductance (speed of energy delivery). Low ESL devices typically have low capacitance. Likewise, higher capacitance devices typically have higher ESLs. This tradeoff between ESL (speed of energy delivery) and capacitance (energy storage) drives the PDN design topology that places the fastest low ESL capacitors as close to the load as possible. Low Inductance MLCCs are found on semiconductor packages and on boards as close as possible to the load. Slowest Capacitors Fastest Capacitors Semiconductor Product VR Bulk Board-Level Package-Level Die-Level Low Inductance Decoupling Capacitors Figure 1 Classic Power Delivery Network (PDN) Architecture LOW INDUCTANCE CHIP CAPACITORS INTERDIGITATED CAPACITORS The key physical characteristic determining equivalent series inductance (ESL) of a capacitor is the size of the current loop it creates. The smaller the current loop, the lower the ESL. A standard surface mount MLCC is rectangular in shape with electrical terminations on its shorter sides. A Low Inductance Chip Capacitor (LICC®) sometimes referred to as Reverse Geometry Capacitor (RGC) has its terminations on the longer side of its rectangular shape. The size of a current loop has the greatest impact on the ESL characteristics of a surface mount capacitor. There is a secondary method for decreasing the ESL of a capacitor. This secondary method uses adjacent opposing current loops to reduce ESL. The InterDigitated Capacitor (IDC) utilizes both primary and secondary methods of reducing inductance. The IDC architecture shrinks the distance between terminations to minimize the current loop size, then further reduces inductance by creating adjacent opposing current loops. When the distance between terminations is reduced, the size of the current loop is reduced. Since the size of the current loop is the primary driver of inductance, an 0306 with a smaller current loop has significantly lower ESL then an 0603. The reduction in ESL varies by EIA size, however, ESL is typically reduced 60% or more with an LICC® versus a standard MLCC. An IDC is one single capacitor with an internal structure that has been optimized for low ESL. Similar to standard MLCC versus LICC®s, the reduction in ESL varies by EIA case size. Typically, for the same EIA size, an IDC delivers an ESL that is at least 80% lower than an MLCC. The Important Information/Disclaimer is incorporated in the catalog where these specifications came from or available online at www.kyocera-avx.com/disclaimer/ by reference and should be reviewed in full before placing any order. TDS-SMDMLCC-0026 | Rev 2 – surface mount ceramic capacitor products – 75 Low Inductance Capacitors Introduction LAND GRID ARRAY (LGA) CAPACITORS LOW INDUCTANCE CHIP ARRAYS (LICA®) Land Grid Array (LGA) capacitors are based on the first Low ESL MLCC technology created to specifically address the design needs of current day Power Delivery Networks (PDNs). This is the 3rd low inductance capacitor technology developed by KYOCERA AVX. LGA technology provides engineers with new options. The LGA internal structure and manufacturing technology eliminates the historic need for a device to be physically small to create small current loops to minimize inductance. The LICA® product family is the result of a joint development effort between KYOCERA AVX and IBM to develop a high performance MLCC family of decoupling capacitors. LICA was introduced in the 1980s and remains the leading choice of designers in high performance semiconductor packages and high reliability board level decoupling applications. The first family of LGA products are 2 terminal devices. A 2 terminal 0306 LGA delivers ESL performance that is equal to or better than an 0306 8 terminal IDC. The 2 terminal 0805 LGA delivers ESL performance that approaches the 0508 8 terminal IDC. New designs that would have used 8 terminal IDCs are moving to 2 terminal LGAs because the layout is easier for a 2 terminal device and manufacturing yield is better for a 2 terminal LGA versus an 8 terminal IDC. LGA technology is also used in a 4 terminal family of products that KYOCERA AVX is sampling and will formerly introduce in 2008. Beyond 2008, there are new multi-terminal LGA product families that will provide even more attractive options for PDN designers. LICA® products are used in 99.999% uptime semiconductor package applications on both ceramic and organic substrates. The C4 solder ball termination option is the perfect compliment to flip-chip packaging technology. Mainframe class CPUs, ultimate performance multi-chip modules, and communications systems that must have the reliability of 5 9’s use LICA®. LICA® products with either Sn/Pb or Pb-free solder balls are used for decoupling in high reliability military and aerospace applications. These LICA® devices are used for decoupling of large pin count FPGAs, ASICs, CPUs, and other high power ICs with low operating voltages. When high reliability decoupling applications require the very lowest ESL capacitors, LICA® products are the best option. 470 nF 0306 Impedance Comparison 1 0306 2T-LGA 0306 LICC 0306 8T-IDC Impedance (ohms) 0603 MLCC 0.1 0.01 0.001 1 10 100 1000 Frequency (MHz) Figure 2 MLCC, LICC®, IDC, and LGA technologies deliver different levels of equivalent series inductance (ESL). 76 The Important Information/Disclaimer is incorporated in the catalog where these specifications came from or available online at www.kyocera-avx.com/disclaimer/ by reference and should be reviewed in full before placing any order. TDS-SMDMLCC-0026 | Rev 2 – surface mount ceramic capacitor products – Low Inductance Ceramic Capacitors LICC® (Low Inductance Chip Capacitors) 0204/0306/0508/0612 RoHS Compliant GENERAL DESCRIPTION The key physical characteristic determining equivalent series inductance (ESL) of a capacitor is the size of the current loop it creates. The smaller the current loop, the lower the ESL. A standard surface mount MLCC is rectangular in shape with electrical terminations on its shorter sides. A Low Inductance Chip Capacitor (LICC®) sometimes referred to as Reverse Geometry Capacitor (RGC) has its terminations on the longer sides of its rectangular shape. The image on the right shows the termination differences between an MLCC and an LICC®. When the distance between terminations is reduced, the size of the current loop is reduced. Since the size of the current loop is the primary driver of inductance, an 0306 with a smaller current loop has significantly lower ESL then an 0603. The reduction in ESL varies by EIA size, however, ESL is typically reduced 60% or more with an LICC® versus a standard MLCC. LICC MLCC KYOCERA AVX LICC® products are available with a lead-free finish of plated Nickel/Tin. PERFORMANCE CHARACTERISTICS Capacitance Tolerances Temperature Coefficient Voltage Ratings K = ±10%; M = ±20% X7R = -55°C to +125°C X5R = -55°C to +85°C X7S = -55°C to +125°C X7R, X5R = ±15%; X7S = ±22% 4, 6.3, 10, 16, 25 VDC Dissipation Factor 4V, 6.3V = 6.5% max; 10V = 5.0% max; 16V = 3.5% max; 25V = 3.0% max Insulation Resistance (@+25°C, RVDC) 100,000MΩ min, or 1,000MΩ per μF min.,whichever is less Operation Temperature Range HOW TO ORDER 0612 Z D 105 M Size 0204 0306 0508 0612 Voltage 4 = 4V 6 = 6.3V Z = 10V Y = 16V 3 = 25V 5 = 50V Dielectric C = X7R D = X5R W = X6S Z = X7S Capacitance Code (In pF) 2 Sig. Digits + Number of Zeros Capacitance Tolerance K = ±10% M = ±20% A T 2 A* Failure Rate Terminations Packaging Available 2 = 7" Reel 4 = 13" Reel Thickness Thickness mm (in) 0.56 (0.022) 0.76 (0.030) 1.02 (0.040) 1.27 (0.050) A = N/A T = Plated Ni 4 = Automotive** and Sn *See the thickness tables on the next page. **Select voltages for Automotive version, contact factory NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers. TYPICAL IMPEDANCE CHARACTERISTICS The Important Information/Disclaimer is incorporated in the catalog where these specifications came from or available online at www.kyocera-avx.com/disclaimer/ by reference and should be reviewed in full before placing any order. TDS-SMDMLCC-0026 | Rev 2 – surface mount ceramic capacitor products – 77 Low Inductance Ceramic Capacitors LICC® (Low Inductance Chip Capacitors) SIZE 0204 Packaging Length Width mm (in.) mm (in.) WVDC 0306 Paper 0.50 ± 0.05 (0.020 ± 0.002) 1.00 ± 0.05 (0.040 ± 0.002) 0204/0306/0508/0612 RoHS Compliant 0508 Paper 0.81 + 0.15 (0.032 ± 0.006) 1.60 + 0.15 (0.063 ± 0.006) PHYSICAL DIMENSIONS AND PAD LAYOUT 0612 Paper/Embossed 1.27 + 0.25 (0.050 ± 0.010) 2.00 + 0.25 (0.080 ± 0.010) Paper/Embossed 1.60 + 0.25 (0.063 ± 0.010) 3.20 + 0.25 (0.126 ± 0.010) Cap Code 102 6.3 10 16 25 6.3 10 16 25 50 6.3 10 16 25 50 Cap 0.001 A A A A V V V V V S S S S V 222 (μF) .0022 A A A A S S S S V S S S S V 332 0.0033 A A A A S S S S V S S S S V 472 0.0047 A A A A S S S S V S S S S V 682 0.0068 A A A A S S S S V S S S S V 103 0.01 A A A A S S S S V S S S S V 153 0.015 A A A A S S S S V S S S S W 223 0.022 A A A A S S S S V S S S S W 333 0.033 A A A S S S V V S S S S W 473 0.047 A A A S S S V A S S S S W 683 0.068 A A A S S S A A S S S V W 104 0.1 A A A S S V A A S S S V W 154 0.15 A A S S V S S S W W 224 0.22 A A S S A S S V W 334 0.33 V V A S S V 474 0.47 V V A 684 0.68 A A A A 105 1 155 1.5 225 335 475 4.7 685 6.8 106 10 4 6.3 10 16 4 C A S S V V V W A V V W W 2.2 A A 3.3 A A L PHYSICAL DIMENSIONS MM (IN.) Size 0204 0306 0508 0612 L 0.50 ± 0.05 (0.020 ± 0.002) 0.81 ± 0.15 (0.032 ± 0.006) 1.27 ± 0.25 (0.050 ± 0.010) 1.60 ± 0.25 (0.063 ± 0.010) W 1.00 ± 0.05 (0.040 ± 0.002) 1.60 ± 0.15 (0.063 ± 0.006) 2.00 ± 0.25 (0.080 ± 0.010) 3.20 ± 0.25 (0.126 ± 0.010) t 0.18 ± 0.08 (0.007 ± 0.003) 0.13 min. (0.005 min.) 0.13 min. (0.005 min.) 0.13 min. (0.005 min.) PAD LAYOUT DIMENSIONS = X5R mm (in.) = X7S mm (in.) = X6S mm (in.) mm (in.) 0204 0306 0508 0612 Code Thickness Code Thickness Code Thickness Code Thickness 0.35 (0.014) T T - See Range Chart for Thickness and Codes Solid = X7R C t W A 0.56 (0.022) S 0.56 (0.022) S 0.56 (0.022) V 0.76 (0.030) V 0.76 (0.030) A 1.02 (0.040) W 1.02 (0.040) A Size 0306 A 0.31 (0.012) B 1.52 (0.060) MM (IN.) C 0.51 (0.020) 0508 0.51 (0.020) 2.03 (0.080) 0.76 (0.030) 0612 0.76 (0.030) 3.05 (0.120) 0.635 (0.025) 0204 1.27 (0.050) “B” C 78 “A” The Important Information/Disclaimer is incorporated in the catalog where these specifications came from or available online at www.kyocera-avx.com/disclaimer/ by reference and should be reviewed in full before placing any order. TDS-SMDMLCC-0026 | Rev 2 – surface mount ceramic capacitor products – C